1. Field of Invention
This invention relates to a test circuit, a wafer having the test circuit within a scribe line of the wafer. This invention also relates to a method, using the test circuit, of monitoring of or conducting defect analysis in a manufacturing process of semiconductor integrated circuits.
2. Description of Related Art
To produce semiconductor integrated circuits, a manufacturing process (wafer process) processes semiconductor substrates (wafers). The manufacturing process includes a large number of process steps. When the wafer process is completed, the wafer becomes a product wafer having a plurality of semiconductor integrated circuit chips (product chips) formed in respective chip areas on the wafer. The chips are, then, separated into individual dies at scribe lines between the chip areas. The dies are, then, packaged to become semiconductor integrated circuit products.
The chip areas are arranged on the wafer in rows and columns. Each of the scribe lines has a shape of a stripe having a constant width. The scribe lines cross with each other to form a shape of a grid. The width of the scribe line should be sufficient large so that the product chips can be easily separated. At the same time, the scribe line should be as narrow as possible to increase the number of product chips produced on a wafer. Typically, the scribe line has the width of 100 to 150 xcexcm.
Test circuits that allow easy and convenient measurement of characteristics of various elements are also formed on the wafer simultaneously with the manufacturing of the product chips. When the wafer process is completed, the product chips are tested before the separation to determine whether each of the product chips functions as required by the specification of the product. At this time, at least some of the test circuits formed on the wafer are also tested to measure the characteristics of the elements and/or to analyze the cause of faults of the product chips.
The result of the test of the test circuit is used to monitor the state of the manufacturing process. That is, for example, if abnormal characteristics are measured, the manufacturing process is checked to determine the cause of the abnormality. The process is adjusted to prevent further occurrence of the abnormality. In addition, when an abnormality is found by the test of the product chips, for example, a yield of the product chips lower than a normal range is found, the test circuits are extensively tested to determine the cause of the abnormality.
FIG. 7A is a circuit diagram illustrating a test circuit 100 of a first conventional example. In the test circuit 100 shown, resistor elements 102, such as contacts between source/drain regions and wires or vias between wires in different wiring layers, are connected in series. The resistance value of the resistor elements 102, such as contacts or vias, is determined from the current flowing through the elements 102 and the potential between pads 104 at both ends of the serially connected resistor elements 102.
Such a configuration is generally referred to as a xe2x80x9ccontact chainxe2x80x9d or xe2x80x9cvia chainxe2x80x9d, and is most frequently used for monitoring manufacturing processes.
FIG. 7B is a circuit diagram illustrating a test circuit 110 of a second conventional example. The test circuit 110 is used for a measuring method called a four-probes method in which four terminals 114, two connected to each end of one resistor element 112, are used. That is, a current is supplied to the resistor element 112 such as a contact or a via, and the potential difference between both ends of the element is measured. Thereby the resistance value can be measured accurately.
These test circuits 100 and 110 have a simplified circuit configuration and use a simplified test methodology, and also require a smaller number of test pads for inputting/outputting signals to/from external measuring equipment. Thereby, the area of the test circuit can be reduced. The test circuit of these conventional examples, therefore, is often formed in the scribe line.
Such an arrangement can eliminate the need for forming the test circuit in the chip area, thereby saving the space available for the product chip. As a result, a number of product chips that can be produced per wafer is increased and the fabrication cost is minimized.
The test circuits of those conventional examples, however, have the following drawbacks.
First, the test circuit 100 of the first conventional example shown in FIG. 5A includes a large number of resistor elements 102 (contacts or vias) arranged in the form of a chain. This arrangement increases the detection sensitivity to an increase in the resistance values of the resistor elements 102 (contacts or vias) when the resistance values of the entire contacts or vias similarly increase.
When the resistance value of only one or a small number of the contacts (or vias) is increased, however, the resistance of the chain hardly increases unless the increase is significant relative to the resistance of the entire chain. Therefore, it is often impossible to detect the increase of the resistance of one or a small number of the contacts (or vias) in the chain.
For example, when the chain includes one hundred resistor elements 102, even if the resistance of one of the resistor elements 102 becomes ten times the value of the other normal resistor elements 102, the resistance of the entire chain becomes merely 109% relative to the normal case. Such increase in the resistance may be regarded as being normal. Thus, merely monitoring the resistance of the entire chain cannot provide a measurement that can be used to detect the abnormality in one or a small number of the contacts (or vias). That is, this type of test circuit has difficulty in detecting a defect in which, for example, the resistance values of only a small fraction of contacts (or vias) are increased.
In fact, in a semiconductor integrated circuit manufacturing process, defects that present abnormalities in only a small fraction of the contacts (or vias) frequently occur. In such cases, a decrease of the yield of the product chips occurs even when the chain resistance falls within a range that is determined to be normal. When the fraction of contacts or vias with the increased resistant is increased to such a degree that the resistance of the chain becomes abnormal, the yield of the chips is drastically reduced in many cases.
Such a tendency has become more pronounced as the minimum feature size of the semiconductor integrated circuit decreases. Accordingly, the test circuit of the first conventional example cannot be satisfactory used in monitoring a semiconductor integrated circuit manufacturing process.
On the other hand, the test circuit 110 of the second conventional example, as shown in FIG. 7B, is suitable to measure the resistance of one resistor element 12, such as a contact (or via). However, it requires four terminals 114 to measure the resistance value of one resistor element 112 and thus requires the same number of pads. Each test pad is typically has a rectangular shape having a size of about 50 to 100 xcexcm on a side. Therefore, arranging only the four pads necessary to measure the resistance of only one resistor element 112 requires a large area.
Thus, for collecting an amount of measurement data sufficient to establish a correlation with the yield of produced chips a large area is needed to arrange a large number of test circuits 110. The test circuit 110, therefore, cannot be realistically used in detecting defects, such as an increase in the resistance of a small fraction of contacts (or vias).
Further, as will be explained in detail later, another test circuit is proposed in a paper presented at ICMTS (International Conference on Microelectronic Test Structures), Vol.8, pp. 57, March 1995, which is incorporated herein by reference in its entirety. In this third conventional example, a large number of elements to be tested, such as contacts, are arranged in the form of an array. Resistance values of individual elements can be measured and evaluated by using a counter, a decoder, and switches.
A similar test circuit is also disclosed in U.S. Pat. No. 4,719,411, which is incorporated herein by reference in its entirety.
However, the size of the third conventional example is large, and is impossible to place in a scribe line on a wafer. Accordingly, the test circuit cannot be placed in a chip area that is otherwise supposed to be allocated to place a product chip. Therefore, the third conventional example can not be suitably used for monitoring a semiconductor manufacturing process.
To overcome the foregoing problems of the related art, a first object of this invention is to provide a test circuit that may be advantageously utilized to monitor a manufacturing process. The test circuit allows detection of an abnormality in a fraction of a large number of elements to be tested. The test circuit includes a pad used for testing the elements that has a dimension suitable to be placed within a scribe line on a semiconductor wafer.
A second object of this invention is to provide a semiconductor product wafer having the test circuit.
A third object of this invention is to provide a method of monitoring a manufacturing process using the test circuit.
To achieve the first object, according to an aspect of this invention a test circuit is provided on a surface of a semiconductor wafer having a plurality of chip areas for placing semiconductor product chips and scribe lines between the chip areas. The test circuit comprises: a plurality of elements to be tested; a selection circuit that sequentially selects at least one of the elements at a time; and a plurality of pads used for testing the elements. The test circuit and the pads are placed within one of the scribe lines.
Similarly, according to another aspect of this invention a semiconductor product wafer is provided that comprises a plurality of product chips placed within respective chip areas arranged on a surface of the semiconductor product wafer and a test circuit. The test circuit comprises: a plurality of elements to be tested; a selection circuit that sequentially selects at least one of the elements at a time; and a plurality of pads used for testing the elements. The test circuit and the pads are placed within one of scribe lines that separate the chip areas.
Preferably, the plurality of pads comprise at least three pads arranged along a longitudinal direction of one of the scribe lines; and the plurality of elements are divided into at least two groups, each including at least two elements. At least two of the groups of elements are separately arranged in respective spaces between adjacent ones of the at least three pads.
Alternatively, the test circuit comprises: a plurality of elements to be tested; and a shift register including a plurality of shift stages, each for selecting a predetermined number of the elements. Each of the shift stages of the shift register and the predetermined number of the elements that can be selected by each of the shift stages are arranged along a direction generally perpendicular to a longitudinal direction of one of the scribe lines to form a unit. The unit has a dimension that can be placed within one of the scribe lines. The test circuit includes at least one block, each comprising a plurality of the units arranged along the longitudinal direction of one of the scribe lines.
According to another aspect of this invention, a method of monitoring a manufacturing process for manufacturing semiconductor product wafers is provided that comprises manufacturing semiconductor product wafers by the manufacturing process. Each of the product wafers comprises: a plurality semiconductor product chips placed in respective chip areas arranged on a surface of the semiconductor product wafer; and a test circuit placed within one of scribe lines between the chip areas. The test circuit comprises a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the elements at a time. The method of monitoring a manufacturing process further comprises: testing each of the elements in the test circuit in at least one of the manufactured semiconductor product wafers; and evaluating results of the testing to monitor the manufacturing process.
Similarly, according to another aspect of this invention, a method of monitoring a manufacturing process for manufacturing semiconductor product wafers is provided that comprises manufacturing semiconductor product wafers including different types of semiconductor product wafers at an arbitrary ratio in an arbitrary order by the manufacturing process. Each of the different types of semiconductor product wafers comprises: a plurality of one of different types of product chips placed in respective chip areas arranged on a surface of the semiconductor product wafer; and a common test circuit placed within one of scribe lines between the chip areas. The common test circuit comprises a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the elements at a time. The method of monitoring a manufacturing process further comprises: selecting a plurality of the manufactured semiconductor product wafers comprising at least two of the different types of the semiconductor product wafers; testing each of the elements in the test circuit in the selected semiconductor product wafers; and evaluating results of the testing to monitor the manufacturing process.
Further, according to another aspect of this invention, a method of monitoring a manufacturing process for manufacturing semiconductor product wafers is provided that comprises manufacturing semiconductor product wafers, each including a plurality of product chips and a test circuit. The test circuit comprises a plurality of elements to be tested and a selection circuit that sequentially selects at least one of the plurality of elements at a time. The method of monitoring a manufacturing process further comprises: testing each of the elements in the test circuit in at least one of the manufactured semiconductor product wafers; evaluating results of the testing; and adjusting the manufacturing process according to the results of the evaluating to prevent occurrence of a decrease in a yield of the product chips.